With the increase in the complexity of hardware systems, it is necessary to be able to deal with system configurations that are increasingly combining models written in a hardware description language, for example of the HDL type (the languages VDHL and Verilog being the most frequently used), and in high level languages of the HLL type (such as C or C++); these languages describe both the elements constituting the hardware and the models constituting the simulation environment.
In the description below, the term “simulation configuration” or “configuration” will be used to designate a set of software models of elements called “components” constituting a global simulation model, the components being connected to one another either directly or through intermediate blocks.
The invention can be used to verify the design of ASICs by simulating their operation, for example in an environment identical to or very similar to their end use; the method for automatic recognition of configurations enables tests to identify the components of a configuration.
In the case of an ASIC that contains a lot of elements and is connected to several external circuits, it is difficult to predict in advance all of the usable configurations and to establish the relationships between the configuration sets that combine various configuration properties and the test sets that are applicable to them. For this reason, the use of certain configuration variants that facilitate debugging is often avoided, since these variants may involve only some of the components, thus simulating only part of the ASIC or its environment.
In order to cover all of the variants of a simulation configuration, it is necessary to have a large number of test variants specific to each configuration. This situation is a potential error source, since each modification and correction of a test must be saved and verified in each variant of the test.